The present invention relates to a solid-state imaging device, and more particularly to the technique for improving the picture quality of an amplification type solid-state image pick-up device.
This application is based on Japanese Patent Applications No. 10-338936, filed Nov. 30, 1998, No. 11-021311, filed Jan. 29, 1999, No. 11-091720, filed Mar. 31, 1999, and No. 11-092964, filed Mar. 31, 1999, the entire content of which is incorporated herein by reference.
In recent years, a new market for image sensors, including digital still cameras, cameras built in personal computers, cellular phones, or the like, and TV conference cameras, has been getting wider. CCDs have been used as image sensors for TV cameras. CCDs, however, are unsuitable for a battery-powered portable apparatus with a camera, because they consume a lot of power. With this backdrop, solid-state image pick-up devices (CMOS image sensors) of the less-power-consumption amplification type (often called MOS type, CMOS type, or APS type) have been developed and commercialized as less-power-consumption solid-state image pick-up devices for mobile gears.
FIG. 1 shows an equivalent circuit of a first conventional amplification-type CMOS image sensor with a read circuit capable of reading a pixel signal pixel by pixel. In FIG. 1, unit cells 1 with one pixel/unit are arranged in a two-dimensional matrix in the cell area (imaging area). Each unit cell 1 is composed of, for example, four transistors Ta, Tb, Tc, Td and one photodiode PD. The ground potential is applied to the anode of the photodiode PD. To the cathode of the photodiode, one end of the read transistor (shutter gate transistor) Td is connected. The gate of the amplification transistor Tb is connected to the other end of the read transistor Td. One end of the vertical selection transistor (row selection transistor) Ta is connected to one end of the amplification transistor Tb. To the gate of the amplification transistor Tb, one end of the reset transistor Tc is connected.
In the cell area, a read line 4 connected in common to the gates of the read transistors Td of the unit cells in the same row, a vertical selection line 6 connected in common to the gates of the individual vertical selection transistors Ta of the unit cells in the same row, and a reset line 7 connected in common to the gates of the individual reset transistors Tc of the unit cells in the same row are formed in such a manner that they correspond to each row. Additionally, in the cell area, a vertical signal line VLIN connected in common to the other end of each amplification transistor Tb in the unit cells in the same column and a power supply line 9 connected in common to the other end of each reset transistor Tc and the other end of each vertical selection transistor Ta in the unit cells in the same column.
Furthermore, outside one end of the cell area, load transistors TL are arranged in the horizontal direction. They are connected between one end of each vertical signal line VLIN and the ground node. In addition, outside the other end of the cell area, noise canceler circuits are arranged in the horizontal direction. Each noise canceler circuit is composed of, for example, two transistors TSH, TCLP, and two capacitors Cc, Ct.
Horizontal selection transistors TH, which are connected to the other end of the corresponding vertical signal line via the corresponding noise canceler circuit, are arranged in the horizontal direction.
A horizontal signal line HLIN is connected in common to the other end of each horizontal selection transistor TH. To the horizontal signal line HLIN, a horizontal reset transistor (not shown) and an output amplification circuit AMP are connected.
Each noise canceler circuit is composed of a sample hold transistor TSH one end of which is connected to the other end of the vertical signal line VLIN, a coupling capacitor Cc one end of which is connected to the other end of the sample hold transistor TSH, a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and the ground node, and a potential clamp transistor TCLP connected to the junction node of the capacitors Cc and Ct. One end of the horizontal transistor TH is connected to the junction node of the capacitors Cc, Ct.
Furthermore, outside the cell area, there are provided a vertical shift register 2 for selecting the vertical selection lines in the cell area in a scanning manner, a horizontal shift register 3 for driving the horizontal selection transistors TH in a scanning manner, a timing generator 10 for generating various timing signals supplied to the noise canceler circuits, a bias generator 11 for generating specific bias potentials at one end of the potential clamp transistor TCLP of the noise canceler circuit, etc., and a pulse selector 2a for selectively controlling the output pulses of the vertical shift register 2 and thereby driving the vertical selection lines 6 in each row in the cell area in a scanning manner.
FIG. 2 is a timing waveform diagram to help explain an example of the operation of the CMOS image sensor shown in FIG. 1. The operation of the CMOS image sensor of FIG. 1 will be described by reference to FIG. 2.
The incident light on each photodiode PD is photoelectrically converted into signal charge, which are stored in the photodiodes PD.
In a horizontal blanking period, when the signal charge in the photodiodes PD is read out from a row of unit cells, the signal (xcfx86ADDR pulse) on the vertical selection line 6 for the line to be selected is turned on to select each vertical signal line VLIN, thereby turning on one row of row selection transistors Ta. This causes a source follower circuit to operate in one row of unit cells. The source follower circuit is composed of a load transistor TL and an amplification transistor Tb to which a power supply potential VDD (e.g., 3.3V) is supplied via a row selection transistor Ta.
Then, the signal (xcfx86RESET pulse) on the reset line 7 is turned on in one row of unit cells, resetting the gate voltage of the amplification transistor Tb to a reference voltage for a specific period of time, which then outputs the reference voltage to the vertical signal line VLIN.
There are variations in the gate potential of the amplification transistor Tb that has been reset, which permits the reset potential of the vertical signal line VLIN at the other end to vary. To reset variations in the reset potential of each vertical signal line VLIN, the driving signal (xcfx86SH pulse) of the sample hold transistor TSH in the noise canceler circuit is turned on in advance (e.g., at the same time when the xcfx86ADDR pulse is turned on) and the driving signal (xcfx86CLP pulse) of the potential clamping transistor TCLP is kept on for a specific period of time after the reference voltage is outputted onto the vertical signal line VLIN, which thereby sets the voltage on the junction node of the capacitors Cc, Ct of the noise canceler circuit to the reference voltage VCC.
Next, after the xcfx86RESET pulse has been turned off, the read line 4 for a specific row is selected and the signal (xcfx86READ pulse) is turned on, turning on the read transistor Td to read the stored charge in the photodiode PD into the gate of the amplification transistor Tb, which varies the gate potential. The amplification transistor Tb outputs the voltage signal corresponding to the amount of change of the gate potential to the corresponding vertical signal line VLIN and noise canceler circuit.
Thereafter, the xcfx86SH pulse in the noise canceler circuit is turned off, which enables the signal component (the signal voltage from which noise has been removed) equivalent to the difference between the reference voltage read as described above and the signal voltage to be stored in the charge storage capacitor Ct even during the effective horizontal scanning period. Specifically, noise, such as variations in the reset potential of each vertical signal line VLIN originating in the cell area, applied to the stage in front of the noise canceler is removed.
Then, the turning off of the xcfx86ADDR pulse turns off the vertical selection transistor Ta, bringing the unit cell into the unselected state, which electrically separates the cell area from each noise canceler circuit.
Thereafter, the driving signals (xcfx86H pulses) of the horizontal selection transistors TH are turned on in sequence during the effective horizontal scanning period, turning on the horizontal selection transistors TH sequentially, which causes the signal voltages on the junction nodes (signal storage nodes) of the capacitors Cc, Ct to be read onto the horizontal signal lines HLIN sequentially. The signal voltages are then amplified by the output amplification circuit AMP and outputted.
In the above operation, the voltage VVLIN of the vertical signal line VLIN is the operating voltage Vm (about 1.5V) of the source follower circuit in the horizontal blanking period. The aforementioned noise canceling operation is performed each time reading is done for one horizontal line.
FIG. 3 is a timing waveform diagram to help explain an example of the operation of the timing generator 10, vertical shift register 2, and pulse selector 2a in FIG. 2. FIG. 3 shows a case where the CMOS sensor of FIG. 1 is used for a system with one field=(1/30) Hz (images with 30 frames/second using one field as one frame).
The timing generator 10 shapes external input pulse signals xcfx86VR and xcfx86HP at a buffer circuit (not shown) and outputs a field-period pulse signal xcfx86VRR and a horizontal-period pulse signal xcfx86HPV to the vertical shift register 2.
The vertical shift register 2 clears all the register outputs to the low (L) level during the period that the pulse signal xcfx86VRR input is at the low (L) level, and then performs a shift operation using pulse signal xcfx86HPV, thereby bringing the output pulse signal ROi (i=1, . . . , n, n+1, . . . ) at the high (H) level in sequence, and inputting the high signals to the pulse selector 2a. 
The pulse selector 2a activates the signal (xcfx86ADDR pulse) of the vertical selection line 6, the signal (xcfx86RESET pulse) of the reset line 7, and the signal (xcfx86READ pulse) of the read line 4 for each line to be selected as shown in FIG. 2, and scans the row to be selected.
As described above, the CMOS image sensor of FIG. 1 outputs, only once in one field period, each output pulse signal ROi of the vertical shift register 2 for selectively controlling a specific row to be selected. Specifically, since the photodiode PD reads the signal only once in one field, it is impossible to perform the electronic shutter operation of controlling the charge storage time of the photodiode PD to control the receiving-light time equivalently.
FIG. 4 schematically shows the configuration of a second conventional CMOS image sensor capable of an electronic shutter operation. The CMOS image sensor comprises, for example, an imaging area (photoelectric conversion section) 14 where unit cells 13 constructed as shown in FIG. 1 are arranged in a two-dimensional matrix, vertical signal lines VLIN formed in the direction of pixel column in the imaging area 14, read-out control vertical selection lines 6 which are formed in the direction of pixel row in the imaging area 14 and performs control in such a manner that it reads the photoelectric conversion signal of each unit cell 13 onto the vertical signal lines VLIN on a pixel row basis, a first vertical selection circuit (read-out vertical shift register) 2 for selectively controlling the read-out control vertical selection lines 6 with read timing in a scanning manner, a horizontal selection transistor TH for selecting the vertical signal line VLIN, a horizontal selection circuit (horizontal selection shift register) 3 for selectively controlling the horizontal selection transistor, a horizontal signal line HLIN for reading the vertical signal line VLIN selected by the horizontal selection shift register 3, and an output amplification circuit AMP for outputting the signal read onto the horizontal signal line HLIN. Although not shown in particular, the second conventional CMOS image sensor is the same as the first one in that the load transistors and noise canceler circuits shown in FIG. 1 are provided in the vicinity of the imaging area 14.
Furthermore, unlike the first conventional CMOS image sensor, the second conventional CMOS image sensor comprises a second vertical selection circuit (electronic shutter vertical shift register) 15 for selectively controlling the read-out control vertical selection lines 6 in a scanning manner with signal storage timing.
Specifically, the electronic shutter vertical shift register 15 is provided separately from the read-out vertical shift register 2 and is designed to scan the row to be selected with specific timing as is the read-out vertical shift register 2. This enables the read-out vertical shift register 2 and electronic shutter vertical shift register 15 to selectively control, twice in one field period, a specific row to be selected. Before the read-out vertical shift register 2 selectively controls the row to be selected and reads the pixel signal onto the vertical signal line VLIN, the electronic shutter shift register 15 selectively controls the row to be selected and starts to store the signal charge. This enables the electronic shutter operation of controlling the light-receiving time equivalently.
The CMOS image sensor of FIG. 4 including a read-out vertical shift register 2 and an electronic shutter vertical shift register 15 as described above has the following problem: when the image sensor performs the variable electronic shutter operation of changing the charge storage time automatically according to, for example, the output level of the light-receiving sensor, a difference in charge storage time occurs between pixel rows in the same frame (or filed) image according to the control of the charge storage time, and the loads on the two vertical shift registers 2, 15 vary.
This problem will be explained below.
FIG. 5 shows an example of the read operation when the row selection timing of the two vertical shift registers 2, 15 in FIG. 4 is fixed. The timing that the electronic shutter vertical shift register 15 selects a row is earlier than the timing that the read-out vertical shift register 2 selects the row. The time by which the former is earlier than the latter is fixed. That is, the difference in the time required to select a row between the two vertical shift registers 2, 15 is always constant. When the row selection timings of the two vertical shift registers 2, 15 are fixed, the read-out vertical shift register 2 and electronic shutter vertical shift register 15 return to the first stage after they have begun to select a certain frame (here, frame=field) and completed the shifting from the first to last stages (that is, the number of pixels in the vertical direction). Then, they start to select the next frame.
Consequently, when the solid-state imaging device of FIG. 4 performs the variable shutter operation of changing the signal (charge) storage time automatically according to, for example, the output level of the light-receiving sensor, thereby changing the light-receiving time equivalently, it cannot start to store the next signal (charge) unless the electronic shutter vertical shift register 15 has finished shifting to the last stage. This puts a limit on the long storage time. If the storage time is not limited, this causes the difference in the charge storage time between pixel rows in one frame or permits the loads on the two vertical shift registers to vary.
In a case where a concrete approach for changing the charge storage time is to change the timing (the timing of the electronic shutter) that the electronic shutter vertical shift register 15 selects a row earlier than the read-out vertical shift register 2, thereby changing the length of the time required to store the signal charge, the problems will be described in detail by reference to FIG. 6.
In FIG. 6, the read control pulse is a signal for staring the shift operation of the read-out vertical shift register 2 and the variable electronic shutter control pulse is a signal for starting the shift operation of the electronic shutter vertical shift register 15.
It is assumed that, when a first frame is selected, an electronic shutter pulse is generated to select a second frame with timing t3 after the shift operation of the electronic shutter vertical shift register 15 is started by an electronic shutter control pulse generated with timing t1 but before the shift operation of the last stage has been completed (or before all of the pixel rows have been selected). The electronic shutter vertical shift register 15 is reset with timing t3 and the shift operation (row selection) is started from the first stage again.
As a result, when the shift operation of the read-out vertical shift register 2 is started by a read control pulse generated with timing t2 and the first frame is read, there arises a difference in the charge storage time between the pixel rows selected and those not selected by the electronic shutter vertical shift register 15 that has started the shift operation with timing t1.
Once the difference in the charge storage time has arisen, the read output level varies, depending on the position of a pixel row, which contributes to the cause of the occurrence of image noise, such as horizontal stripes, when the output signal of the solid-state imaging device is displayed on the screen of the image display device.
At timing t4, a total of two pixel rows are selected: one is the selected row at the electronic shutter vertical shift register 15 that has started the shift operation at timing t3 and the other is the selected row at the read-out vertical shift register 2 that started the shift operation with timing t2. These two pixel rows make the loads on the two vertical shift registers 2, 15.
In contrast, at timing t6, the selection of row at the electronic shutter vertical shift register 15 that has started the shift operation with timing t3 has been completed already and only one pixel row is selected by the read-out vertical shift register 2 that has started the shift operation with timing t5. As a result, the single pixel row makes the load on the two vertical shift registers 2, 15.
When the loads on the two vertical shift registers 2, 15 varies, depending on the electronic shutter timing, this causes fluctuations in the voltage of the power supply line of the solid-state imaging device. When the output of the solid-state imaging device is displayed on the screen of the image display device, horizontal stripes appear, which contributes to serious degradation of picture quality.
The problems of the occurrence of a difference in charge storage time between pixel rows according to the length of the charge storage time and the variation of the loads on the two vertical shift register 2, 15 are encountered when the variable electronic shutter operation is performed by not only the CMOS solid-state imaging device but also the CCD solid-state imaging device.
It is important for the image pick-up device not to degrade the image quality due to hand shake. An example of a hand shake correction of the conventional CMOS image sensor is described in the Japanese Patent Disclosure No. 2-231873. Only part of the whole light receiving area is used as an imaging area and the hand shake correction is performed by shifting the imaging area based on the amount of hand shaking. However, the brightness of the image of one field (or frame) varies due to the variation of the signal charge storage time of each horizontal line in one field (or frame) if the imaging area is shifted. This drawback is solved by a technique disclosed in U.S. Pat. No. 5,894,325(Yonemoto). In this reference, a second vertical shift register for an electric shutter operation is provided in addition to a first vertical shift register for reading out the signal. The signal charge storage time is controlled by adjusting the operation timings of the first and the second vertical shift registers. However, it is not possible to start storing the signal charge for the next field before the read-out of the current field is completed so that the signal charge storage time cannot be freely controlled.
Accordingly, it is an object of the present invention to overcome the above problems by providing a solid-state imaging device which prevents a difference in charge storage time between pixel rows in the same field (or frame) from arising according to the length of charge storage time when the charge storage time is varied field by field (or frame by frame) to perform a variable electronic shutter operation.
Another object of the present invention is to provide a solid-state imaging device which prevents the loads on the read-out vertical shift register and electronic shutter shift register from fluctuating when the variable electronic shutter operation is performed.
Further object of the present invention is to provide a solid-state imaging device which suppresses the occurrence of image noise, such as lateral stripes, on the display screen for the output signal when the variable electronic shutter operation is performed.
Still another object of the present invention is to provide a solid-state imaging device capable of preventing noise from coming in from the wiring around the pixels through capacitive coupling, when the signal photoelectrically converted and stored in the pixels is read.
Still further object of the present invention is to provide a solid-state imaging device capable of preventing the degradation of the image quality due to hand shake.
According to the present invention, there is provided a solid-state imaging device comprising:
an image pickup section with a light-receiving surface whose area is greater than an imaging area for outputting an image signal;
a vertical register circuit for driving pixel rows in the image pickup section;
a horizontal register circuit for driving pixel columns in the image pickup section; and
a timing generator for supplying a signal charge time control signal to the vertical register circuit, wherein the vertical register circuit is capable of simultaneously selecting three or more pixel rows during a horizontal blanking period.
According to the present invention, there is provided another solid-state imaging device comprising:
an imaging area including unit cells arranged on a semiconductor substrate two-dimensionally to form pixel rows, each of the unit cells being composed of a photoelectric converting element for photoelectrically converting incident light on a pixel and storing charge, a read section for reading the stored charge to a sense node, an amplification section for amplifying the read-out charge, and a vertical selection element for causing the amplification section to output a signal;
read lines, which are provided in a horizontal direction so as to correspond to the pixel rows respectively in the imaging area, for transferring a read driving signal for driving the read sections of the unit cells in the corresponding pixel rows;
vertical selection lines, which are provided in a horizontal direction so as to correspond to the respective pixel rows in the imaging area, for transferring a row selection driving signal for driving the vertical selection elements of the unit cells in the corresponding pixel rows;
a vertical driving circuit for selectively supplying the read driving signal to the read lines to drive the read sections and for selectively supplying the row selection driving signal to the vertical selection lines to drive the vertical selection elements;
a row selection circuit for controlling the vertical driving circuit in such a manner that the read sections in each pixel row in the imaging area are driven with desired signal storage timing and with signal read timing in that order, the row selection circuit including a first row selector for causing the vertical driving circuit to drive the read sections in each pixel row with the signal read timing and at least two second row selectors for causing the vertical driving circuit to drive the read sections in each pixel row with the signal storage timing; and
vertical signal lines, which are provided so as to correspond to the pixel rows respectively in the imaging area, for transferring in a vertical direction an signal outputted from each unit cell in the pixel rows sequentially driven by the vertical driving circuit.
According to the present invention, there is provided a further solid-state imaging device which performs an electronic shutter operation by sequentially driving a read control wire with a desired signal storage timing and a desired signal read timing and outputting a signal read with the desired signal read timing when a stored charge is read out from a photoelectric converting element in unit cells two-dimensionally arranged in an imaging area on a semiconductor substrate, wherein a voltage of another wire adjacent to the read control wire in the vicinity of the photoelectric converting element at the desired signal storage timing is substantially the same as that at the desired signal read timing.
According to the present invention, there is provided a still another solid-state imaging device including an imaging area formed of unit cells each having two pixels and two-dimensionally arranged on a semiconductor substrate, wherein charges stored in two pixels are sequentially read out and a voltage of another wire adjacent to the read control wire in the vicinity of the unit cells when the charge stored in one pixel is read out is substantially the same as that when the charge stored in the other pixel is read out.
According to the present invention, there is provided a still further solid-state imaging device comprising:
an imaging area including unit cells arranged on a semiconductor substrate two-dimensionally to form pixel rows, each of the unit cells being composed of a photoelectric converting element for photoelectrically converting incident light on a pixel and storing charge, a read section for reading the stored charge to a sense node, an amplification section for amplifying the read-out charge, and a vertical selection element for causing the amplification section to output a signal, the imaging area including plural pixel rows for reading signals and at least two dummy pixel rows;
read lines, which are provided in a horizontal direction so as to correspond to the pixel rows respectively in the imaging area, for transferring a read driving signal for driving the read sections of the unit cells in the corresponding pixel rows;
vertical selection lines, which are provided in a horizontal direction so as to correspond to the respective pixel rows in the imaging area, for transferring a row selection driving signal for driving the vertical selection elements of the unit cells in the corresponding pixel rows;
a vertical driving circuit for selectively supplying the read driving signal to the read lines to drive the read sections and for selectively supplying the row selection driving signal to the vertical selection lines to drive the vertical selection elements;
a row selection circuit for controlling the vertical driving circuit in such a manner that the read sections in each pixel row in the imaging area are driven with desired signal storage timing and with signal read timing in that order; and
vertical signal lines, which are provided so as to correspond to the pixel rows respectively in the imaging area, for transferring in a vertical direction an signal outputted from each unit cell in the pixel rows sequentially driven by the vertical driving circuit, wherein the row selection circuit controls the vertical driving circuit such that the stored charge is read out from the unit cells of the plural pixel rows, one of the at least two dummy pixel rows is driven, charge is stored in the unit cells of the plural pixel rows, and then the other of the at least two dummy pixel rows is driven.
According to the present invention, there is provided a still further solid-state imaging device including unit cells which are two-dimensionally arranged in directions of row and column and generate an electric signal according to the amount of incident light, vertical signal lines for reading an electric signal from the unit cells column by column, a vertical control section for controlling a reading of the electric signal generated at the unit cells onto the vertical signal lines, and a horizontal control section for controlling a transfer in the horizontal direction of the electric signal read by the vertical control section onto the vertical signal lines, the solid-state imaging device comprising:
a gain correction factor calculator for calculating a gain correction factor for fluctuations in luminance in the amount of incident light to the unit cells for each row from reading of a first signal from the unit cells and reading of a second signal from the unit cells time xcex94t later than the reading time of the first electric signal; and
an arithmetic operating circuit for correcting the second signal on the basis of the calculated gain correction factor.
According to the present invention, there is provided a still further solid-state imaging device including unit cells which are two-dimensionally arranged in directions of row and column and generate an electric signal according to the amount of incident light, vertical signal lines for reading an electric signal from the unit cells column by column, a vertical control section for controlling a reading of the electric signal generated at the unit cells onto the vertical signal lines, and a horizontal control section for controlling a transfer in the horizontal direction of the electric signal read by the vertical control section onto the vertical signal lines, the solid-state imaging device comprising;
a calculation element for calculating more than one difference xcex94S between a first signal S read from the unit cells and a second signal Sxe2x80x3 read from the unit cells from which the first signal S has been read at time xcex94txe2x80x2 later than the reading time of the first signal S, while changing the time xcex94txe2x80x2, and
a determination element for determining the period of fluctuations in luminance by comparing more than one xcex94S obtained by changing the time xcex94txe2x80x2.
Additional objects and advantages of the present invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the present invention.
The objects and advantages of the present invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.